Circuit for synchronizing signals during the exchange of information between circuits

ABSTRACT

A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.

BACKGROUND OF THE INVENTION Field of the Invention

[0001] The invention relates to a circuit for synchronizing signalsduring the exchange of information between circuits, in particularbetween computer chips, of a system of circuits, having a delay lockedloop (DLL) circuit for synchronizing the internal clock between arespective circuit and the external clock of the circuit systemaccording to the phase difference between these two clocks in a mannerdependent on phase changes in the signals. The response sensitivity ofthe DLL circuit being defined by a filter, which enables a renewedsynchronization only after the arrival of a plurality of phase changeevents.

[0002] Computer chips are operated with ever faster clock frequencies.Information is exchanged between the computer chips with signals thathave to comply with defined timing specifications. The timing marginsavailable in this case decrease at increasingly faster clockfrequencies. Therefore, with increasingly faster clock frequencies, thesignals which are transmitted in the context of the exchange ofinformation between the computer chips have to be synchronized ever moreaccurately with respect to one another.

[0003] The task of the synchronization discussed is performed by a delaylocked loop circuit (referred to below as a DLL circuit for short)implemented on the respective computer chip. The DLL circuitsynchronizes the internal clock within the computer chip with the clockof the circuit system or the system of computer chips. For this purpose,the DLL circuit contains a phase detector which determines the phasedifference between the internal clock of the computer chip and theexternal clock of the overall system. Furthermore, the DLL circuitcontains variable delay elements (also referred to below as VCDL) thatare connected or disconnected as required.

[0004] In order that the DLL circuit does not connect or disconnectdelay elements in the case of every phase change, which, in principle,can occur in every clock cycle, a filter is provided in the DLL circuit.The function of the filter is to drive an output signal only afterrepeated arrival of an input signal and thus to trigger thesynchronization by the DLL circuit only after a specific number of clockcycles. The filter is generally implemented on the basis of a pluralityof counters and it determines, as discussed above, the sensitivity ofthe DLL circuit to phase changes. The number of counters in the filterdepends on the specific computer chip and the overall system of computerchips and has hitherto formed an invariable quantity.

SUMMARY OF THE INVENTION

[0005] It is accordingly an object of the invention to provide a circuitfor synchronizing signals during the exchange of information betweencircuits which overcomes the above-mentioned disadvantages of the priorart devices of this general type, whose sensitivity to phase changes isadjustable.

[0006] With the foregoing and other objects in view there is provided,in accordance with the invention, a configuration for synchronizingsignals during an exchange of information between circuits of a circuitsystem. The configuration contains a delay locked loop circuit forsynchronizing an internal clock of one of the circuits and an externalclock of the circuit system according to a phase difference between theinternal clock and the external clock in a manner dependent on phasechanges in the signals. The delay locked loop circuit has a filter fordefining a response sensitivity of the delay locked loop circuit. Thefilter enables a renewed synchronization only after an arrival of aplurality of phase change events. The filter has a variableconfiguration and includes a plurality of counters for generating asynchronization enable signal, and a logic circuit connected to andactivating/deactivating the counters.

[0007] Accordingly, in contrast to the prior art, which provides a fixedfilter configuration, according to the invention the filter contained inthe DLL circuit is of a variable configuration. Depending on theconstruction of the filter, various measures are taken intoconsideration for altering the filter characteristics. For the casewhere the filter contains a plurality of counters for generating asynchronization enable signal, the invention provides a logic circuitfor activating/deactivating the counters.

[0008] The setting of the sensitivity of the DLL circuit to phasechanges of input signals plays a significant part in the preliminarystages of the enabling of computer chips or generally of circuits whichrequire a synchronization in order to set the synchronization to therequired response sensitivity in a targeted manner before the controloperation with a defined response sensitivity. As soon as this settinghas been effected, the logic circuit for setting the responsesensitivity of the DLL circuit can be deactivated, if appropriate byfuses.

[0009] In addition to the principal advantage according to which thesynchronization between the computer chips of the system of computerchips can be optimally set according to the invention in the preliminarystages of the control operation, a further advantage is afforded in areduction in the lock time of the DLL circuit, i.e. a reduction in theduration until the phasing of the DLL circuit. Furthermore, theinvention achieves regulation of the DLL current consumption, which iscritically determined by the number of time delay changes per unit timeand, on account of the filter components that are only partly activatedaccording to the invention, is lower than in the case of constantoperation of all the filter components. Finally, the synchronizationcircuit configured according to the invention ensures optimization ofthe control speed of the overall system containing circuits or computerchips.

[0010] When the filter is constructed from a plurality of counters, theactivation/deactivation thereof for the purpose of changing the filtercharacteristic can be achieved without a great outlay by a transfer gateconnected upstream of the respective counter of the filter. The transfergate can be configured in various ways. It is preferably configured toswitch on/off a specific counter or a group of counters while theremaining counters or the remaining counter remain or remains switchedon. The transfer gate can be implemented cost-effectively by an n-/p-FETcombination.

[0011] In accordance with an added feature of the invention, the logiccircuit can be put into a test mode for setting the response sensitivityfor optimizing synchronization before a control operation with a definedresponse sensitivity of the configuration is performed.

[0012] In accordance with another feature of the invention, the logiccircuit has transfer gates connected to and switching on/off thecounters in a targeted manner.

[0013] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0014] Although the invention is illustrated and described herein asembodied in a circuit for synchronizing signals during the exchange ofinformation between circuits, it is nevertheless not intended to belimited to the details shown, since various modifications and structuralchanges may be made therein without departing from the spirit of theinvention and within the scope and range of equivalents of the claims.

[0015] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a block diagram of a basic construction of a DLL circuitaccording to the invention;

[0017]FIG. 2 is a block diagram of an embodiment of a variable filter ofthe DLL circuit shown in FIG. 1;

[0018]FIG. 3 is a block diagram of a further embodiment of the variablefilter of the DLL circuit shown in FIG. 1; and

[0019]FIG. 4 is a schematic diagram of a transfer gate for switchingon/off, in a targeted manner, counters of the filter shown in FIG. 2 andFIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1 thereof, there is shown a general constructionof a delay locked loop (DLL) circuit for the synchronization of signalsduring the exchange of information between circuits. The DLL circuitspecifically serves for the synchronization of an internal clock betweena respective circuit, for example a computer chip, and an external clockof a system containing a plurality of circuits or computer chipsaccording to the phase difference between the two clocks depending onphase changes of the synchronized signals. For this purpose, in additionto a first invariable delay element T_(I) at an input of the circuit andan invariable delay element T₀ at an output of the circuit, the DLLcircuit contains, between these two invariable delay elements T_(I), T₀,variable delay elements designated by VCDL.

[0021] The response sensitivity of the DLL circuit is defined by afilter 10, whose output signal acts on the delay elements VCDL and whichis acted on by a phase detector PD on the input side. For its part, thephase detector PD is acted on, on the input side, by the output of theinvariable delay element T_(I) and, on the other hand, via a furtherdelay element dT, by the delay elements VCDL.

[0022] The function of the filter 10 consists in driving an outputsignal only after a defined repeated arrival of an input signal and thusin determining the response sensitivity of the DLL circuit.

[0023] The filter 10 is usually realized with a plurality of countersthat are connected in series and through which passes the output signalof the phase detector PD. Such an implementation of the filter 10, butwith the filter characteristic of the filter 10 being of a variableconfiguration according to the invention, is shown in FIG. 2.Accordingly, the filter 10 contains four counters 11, 12, 13 and 14. Thecounters 11 to 14 are connected in series between the input and theoutput of the filter 10. In this respect, the construction of the filter10 corresponds to the construction of previous filters in DLL circuits.In a departure therefrom, the invention provides, in a test mode whichserves for setting the response sensitivity of the DLL circuit, for oneor more of the counters 11 to 14 to be switched on or off in a targetedmanner in order to optimize the synchronization, the control operationwith a defined response sensitivity of the circuit.

[0024] In the embodiment of the filter 10 that is shown in FIG. 2, alogic circuit is provided which performs the targeted switching on/offof the counters 11 to 14. The logic circuit contains a first logic unit15, which can be controlled by a test mode signal TM and whose fouroutputs are assigned to the counters 11, 12, 13 and 14. Moreover, thelogic circuit contains a second logic unit 16 upstream of the output ofthe filter 10 and four transfer gates 17, 18, 19 and 20 at the inputs ofthe counters 11 to 14. A control signal of each of the transfer gates 17to 20 is acted on by a respective output signal of the first logic unit15. Furthermore, the four transfer gates 17 to 20 have outputs which areconnected either to four inputs of the logic unit 16, or to thedownstream counters 11 to 14.

[0025] The method of operation of the logic circuit provides for signalsproceeding from the first logic unit 15 to activate or not activate thetransfer gates 17 to 20 upstream of the counters 11 to 14. If a transfergate is activated with respect to the counter connected downstream, e.g.only the transfer gates 17 and 18 are activated with respect to thecounters connected downstream, whereas the transfer gates 19 and 20 arenot activated, so that only the first two counters 11 and 12 in thefilter 10 are active. This affects a greater sensitivity than in thecase where all four counters 11 to 14 are active or their transfer gatesare activated.

[0026] The phase detector PD outputs a clock signal depending on thephase difference between the signals that are fed to the delay elementsand output by the delay elements. Depending on the switching position ofthe first transfer gate 17, the clock signal is fed either to the secondlogic unit 16 or to the first counter 11. The first counter 11 counts upas far as a maximum count depending on the number of clock signals. Uponreaching the maximum count, the first counter 11 outputs a clock signalto the second transfer gate 18. Depending on the switching position ofthe second transfer gate 18, the clock signal is passed to the secondlogic unit 16 or the second counter 12. The second counter 12 operateslike the first counter 11. After reaching the maximum count, the secondcounter 12 outputs a clock signal and forwards it to the third transfergate 19. Depending on the switching position, the third transfer gate 19passes the clock signal to the second logic unit 16 or to the thirdcounter 13. The third and fourth counters 13, 14 function like the firstand second counters. The fourth and fifth transfer gates function likethe second and third transfer gates. The second logic unit 16 isconfigured as an OR gate and forwards a clock signal obtained from thetransfer gates or from the fourth counter 14 to the output FOUT. In asimple embodiment, when a clock signal is obtained from the delayelement VCDL, a further delay element is connected into the signal pathbetween input IN and output OUT. However, it is also possible to providea time window in which the clock signals output by the second logic unit16 are counted and, depending on the number, the number of delayelements to be connected into the signal path is defined.

[0027] An alternative embodiment of the filter 10 of FIG. 2 is shown inFIG. 3. A filter 10′ contains three series-connected counters 21, 22 and23, upstream of which there is again connected in each case a transfergate 24, 25 and 26, respectively. In this embodiment, the logic circuitcontains a logic unit 27, controlled by the test mode signal TM, fordriving the transfer gates 24, 25 and 26 and also logic units 28, 29 and30, which are connected downstream of the respective counters 21, 22, 23and are each acted on by an output signal of the associated transfergate 24, 25 and 26, respectively.

[0028] The method of operation of the filter 10′ provides that the logicunit 27 can switch the counters on or off by the transfer gates. By wayof example the counter 22 by the transfer gate 25.

[0029] The transfer gates 24 to 26 switch a supplied clock signal,depending on the switching position, either to the assigned counter 21,22, 23 or to the assigned logic 28, 29, 30. The logic modules 28, 29, 30are embodied as OR gates and forward the supplied clock signal to therespective connected transfer gates 25, 26 or to the output FOUT.

[0030] The embodiments of the filters 10, 10′ that are shown in FIGS. 2and 3 are not restricted to the abovementioned numbers of four and threecounters, respectively. Moreover, FIGS. 2 and 3 only show exemplaryembodiments of the logic driving of the counters of the filter.

[0031]FIG. 4 diagrammatically shows an example of an embodiment of atransfer gate that is used in the filters 10, 10′ configured accordingto the invention. Accordingly, the transfer gate contains an n-/p-FETcombination with an n-FET 31 and a p-FET 32.

We claim:
 1. A configuration for synchronizing signals during anexchange of information between circuits of a circuit system, theconfiguration comprising: a delay locked loop circuit for synchronizingan internal clock of one of the circuits and an external clock of thecircuit system according to a phase difference between the internalclock and the external clock in a manner dependent on phase changes inthe signals, said delay locked loop circuit having a filter for defininga response sensitivity of the delay locked loop circuit, said filterenabling a renewed synchronization only after an arrival of a pluralityof phase change events, said filter having a variable configuration andincludes: a plurality of counters for generating a synchronizationenable signal; and a logic circuit connected to andactivating/deactivating said counters.
 2. The configuration according toclaim 1, wherein said logic circuit can be put into a test mode forsetting the response sensitivity for optimizing synchronization before acontrol operation with a defined response sensitivity of theconfiguration is performed.
 3. The configuration according to claim 1,wherein said logic circuit has transfer gates connected to and switchingon/off said counters in a targeted manner.
 4. The configurationaccording to claim 3, wherein said transfer gates switch on/off aspecific counter of said counters or a group of said counters, while anyremaining ones of said counters remain switched on.
 5. The circuitaccording to claim 3, wherein said transfer gates have an n-/p-FETcombination.
 6. The configuration according to claim 1, wherein thecircuits are computer chips.